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Technical Background: Optical Interconnection Driven by AI Compute Clusters
Existing Limitations of Traditional Data Center Interconnection
The large-scale deployment of GPU clusters for large language model training has raised higher requirements for data center transmission performance. Conventional data centers adopt a combination of copper traces and pluggable optical transceivers, which present three prominent technical limitations. First, long-distance copper transmission on printed circuit boards causes significant signal attenuation, requiring digital signal processors (DSP) for signal compensation and resulting in relatively high power consumption. Second, the port density of traditional switches is physically constrained by front-panel layout, making it difficult to support bandwidth iteration beyond 100 Tb/s. Third, electrical signals suffer from unstable latency, which compromises gradient synchronization efficiency during large-scale GPU collaborative computing.
In large-scale GPU-based AI computing facilities, optical interconnection power consumption accounts for approximately 10% of total computing power consumption. The inherent drawbacks of traditional interconnection solutions become increasingly obvious, creating demand for underlying architectural optimization.
Industrial Positioning and Development of CPO Technology
Co-packaged Optics (CPO) is a heterogeneous optoelectronic integration technology that integrates optical components with computing chips through advanced packaging processes. The year 2026 is widely regarded as the initial commercialization year of CPO. The mass production of TSMC COUPE 3D packaging process and the launch of commercial switches from Broadcom and NVIDIA mark the transition of CPO from laboratory verification to industrial deployment. As one of the viable technical solutions for hyper-scale AI data centers, CPO balances low power consumption, high bandwidth density and stable low latency.
CPO Concepts: Definition, Design Logic and Technical Positioning
Academic and Plain-language Definition
● Academic Definition: Leveraging 2.5D and 3D advanced packaging technologies, CPO integrates photonic integrated circuits (PIC) and electronic integrated circuits (EIC) on the same packaging substrate of ASIC switches or AI accelerators. It shortens electrical interconnections to the millimeter level and removes traditional DSP retimers to realize direct chip-level optoelectronic conversion.
● Plain-language Definition: CPO embeds external optical transceivers into switch chips to reduce physical transmission distance between chips and optical fibers. By eliminating redundant signal processing components, the hardware transmission structure is simplified for improved power efficiency and data transmission speed.
Underlying Design Philosophy
CPO follows the widely recognized design principle of short electrical path, long optical path. Electric signals with poor high-frequency stability are confined to millimeter-scale short-distance transmission to avoid copper-based signal loss and distortion. Optical fibers are applied for long-distance high-capacity data transmission to ensure transmission stability and coverage, restructuring the fundamental interconnection framework of modern data centers.
Quantitative Evaluation of CPO Core Value
Compared with conventional pluggable optical modules, CPO demonstrates measurable performance improvements: interconnection power consumption reduced by 60%-70%, bandwidth density increased by more than 100%, and decreased signal distortion rate. For large-scale GPU clusters, CPO helps cut one-time hardware construction costs by 3%-21% and delivers more prominent advantages in long-term operational cost control.
CPO Hardware Architecture and Component Analysis
The CPO system adopts a highly compact heterogeneous integrated physical structure, containing customized passive optical assemblies such as Fiber Array Unit (FAU) and Fiber Shuffle for internal dense optical routing. Different from discrete pluggable transceivers, all photonic and electronic dies are enclosed within a single organic packaging substrate, forming an integrated optoelectronic co-packaged structure with millimeter-scale interconnection. The overall hardware structure is divided into four mutually independent and collaboratively functional layers: computing control layer, optoelectronic conversion layer, light source supply layer, and optical fiber transmission layer. Each layer contains standardized dies, high-density fiber routing components, passive optical fixtures, and thermal conductive structures. The internal physical composition, stacking form, and structural characteristics are described in detail below.
Introduction to Four Architectural Layers in CPO
● Computing Control Layer (Top Layer): This layer consists of switching ASIC or AI accelerator dies manufactured by advanced CMOS processes. The chip contains high-speed SerDes arrays, routing logic units, and power management circuits. The bottom surface of the ASIC die is connected to the silicon interposer through micro-bumps with a bump pitch less than 50μm. This layer undertakes data forwarding, packet scheduling, and electrical signal driving, acting as the logical control center of the entire CPO structure.
● Optoelectronic Conversion Layer (Middle Core Layer): Serving as the core functional layer of CPO, this layer comprises EIC (Electronic Integrated Circuit) and PIC (Photonic Integrated Circuit). In the 3D stacking structure, the EIC is vertically stacked on the surface of the PIC through ultra-thin copper pillars; in the 2.5D structure, the two dies are placed side-by-side on a silicon interposer. The PIC integrates silicon-based waveguides, micro-ring modulators, photodetectors, and optical power splitters. The EIC provides high-speed differential driving signals for modulators and completes analog signal amplification and sampling. The lateral spacing between EIC and PIC is controlled within 100–300μm to minimize parasitic impedance.
● Light Source Supply Layer (External Isolated Layer): Differing from embedded laser schemes, mainstream commercial CPO adopts an external light source structure. The discrete laser module is placed outside the packaging shell and connected to the on-chip waveguide through fiber arrays. The laser emits multi-wavelength continuous light, which is transmitted into the PIC via passive coupling structures. The external placement physically isolates high-heat laser components from photonic chips, forming an independent thermal management structure and avoiding wavelength drift of silicon photonic devices caused by thermal crosstalk.
● Optical Fiber Transmission Layer (Bottom Passive Layer): This layer is composed of high-precision passive optical assemblies, including Fiber Array Unit (FAU), Fiber Shuffle rearrangement arrays, polarization-maintaining optical fibers, edge coupling grooves, and grating couplers. FAU provides fixed high-precision alignment for optical channels, while Fiber Shuffle reorganizes dense fiber routing to match non-uniform on-chip waveguide distribution. All fiber arrays are bonded on the packaging substrate with micron-level alignment tolerance. This layer undertakes long-distance optical signal transmission, channel rearrangement, and polarization maintenance, realizing stable optical interconnection between distributed CPO packaging devices.
Introduction to Six Hardware Components in CPO
● Switch ASIC / AI Accelerator: Core routing and computing chips. Broadcom Tomahawk 6 supports a bandwidth of 102.4 Tb/s, while NVIDIA Quantum-X provides 51.2 Tb/s InfiniBand transmission for diversified computing networking scenarios.
● Photonic Integrated Circuit (PIC): Silicon photonic chips integrated with waveguides, modulators and photodetectors. Mainstream modulators include Mach-Zehnder Modulators (MZM), Micro-Ring Modulators (MRM) and Electro-Absorption Modulators (EAM). MRM is widely adopted in commercial products due to its low power consumption characteristics.
● Electronic Integrated Circuit (EIC): CMOS-based chips embedded with SerDes, drive control and power management units, ensuring signal matching between ASIC and PIC.
● Optical Engine: Integrated optoelectronic modules combining PIC, EIC and optical fiber arrays, with single-engine bandwidth ranging from 1.6 Tb/s to 6.4 Tb/s, serving as the core carrier of optoelectronic conversion.
● External Laser Source (ELS): Discrete laser modules supporting multi-wavelength output. Typical products such as Ayar Labs SuperNova provide 16 wavelength channels. The external structure optimizes thermal management and supports independent replacement.
● Optical Fiber Connectors: Divided into edge coupling and surface coupling solutions. Edge coupling features low insertion loss with permanent bonding; surface coupling allows detachable assembly and has higher alignment tolerance. Corning GlassBridge and Marvell metal couplers are mainstream commercial accessories.
CPO Packaging Technology and Signal Transmission Mechanism
Mainstream Packaging Technologies and Engineering Trade-offs
Current commercial CPO products mainly adopt two advanced packaging solutions: 2.5D integration and 3D stacking. Each solution has differentiated characteristics in cost and performance:
● 2.5D Integration Process: EIC and PIC are placed side by side on a silicon interposer. This mature process features low manufacturing cost and high yield rate, with moderate transmission performance caused by parasitic inductance. It is commonly applied in mid-range commercial switches, represented by the first-generation Santec CPO switches.
● 3D Hybrid Stacking Process: EIC is vertically stacked on PIC to minimize electrical transmission paths, achieving lower power consumption and higher bandwidth. The process faces higher technical difficulty, manufacturing cost and heat dissipation pressure. TSMC COUPE process is the industry benchmark, adopted by high-end CPO switches from NVIDIA and Broadcom.
Four-stage Signal Transmission Workflow
The CPO transmission system features simplified links without redundant signal processing procedures. The complete transmission process includes four phases with controllable overall latency:
● Electrical Signal Transmission: The ASIC chip transmits high-speed electrical signals to EIC through millimeter-scale copper lines inside the package, with a single-channel rate ranging from 100 to 200 Gb/s without additional signal compensation.
● Optoelectronic Conversion: EIC drives internal PIC modulators to complete electro-to-optical signal conversion; photodetectors realize reverse decoding at the receiving end to support bidirectional transmission.
● Optical Signal Transmission: Optical signals are transmitted from on-chip waveguides to optical fiber arrays, and then transmitted over long distances through external optical fiber links via couplers.
● Continuous Light Supply: External lasers output stable light beams, which are allocated to each optical engine through optical splitters to realize heat isolation and resource redundancy.
CPO Technical Advantages and Engineering Challenges
Major Technical Advantages
● Low Power Consumption for Operational Cost Reduction: A conventional 30 W pluggable transceiver can be replaced by a 9 W CPO link, reducing power consumption by approximately 70%. The overall network power consumption of supercomputing clusters can be reduced by 3.5 times. The power-saving effect comes from shortened copper transmission paths and the elimination of high-power DSP chips, effectively cutting long-term electricity and cooling expenditures for large-scale clusters.
● Ultra-high Bandwidth Breaking Physical Constraints: Supported by 3D stacked silicon photonic technology, the maximum bandwidth of a single optical engine reaches 6.4 Tb/s, and the switch bandwidth density ranges from 51.2 Tb/s to 102.4 Tb/s. CPO breaks through the front-panel port limitation of traditional switches, enabling horizontal bandwidth expansion by adding optical engines to adapt to iterative upgrades of AI computing power.
● Low Latency and High Stability for Distributed Computing: Millimeter-level electrical paths eliminate redundant signal equalization and retiming processes, improving signal integrity. In multi-GPU collaborative training tasks, CPO reduces latency fluctuation and enhances gradient synchronization consistency to optimize large model training efficiency.
● Flexible Networking for Large-scale Cluster Layout: Copper cables only maintain effective transmission within 1-2 meters at high speed, while CPO optical links support long-distance cross-rack and cross-data-center transmission without repeaters. The flexible network architecture adapts to high-performance topologies such as fat-tree and dragonfly, matching the layout requirements of million-scale GPU clusters.
Existing Engineering Constraints and Trade-offs
● Strict Heat Dissipation Requirements: Silicon photonic devices are highly sensitive to temperature fluctuations, and modulators are prone to wavelength drift under heat variation. The close integration of optical engines and high-heat ASICs causes localized heat accumulation, making traditional air cooling insufficient. Liquid cooling cold plates are required, increasing hardware modification and structural complexity.
● Complex Operation of High-density Optical Fibers: High-end CPO switches are equipped with tens of thousands of optical fibers, bringing challenges to cable management and bending radius control. Permanently bonded optical fibers feature low loss but poor maintainability; detachable connectors simplify maintenance yet increase insertion loss. The industry generally makes compromises between transmission performance and operational difficulty.
● Immature Manufacturing and Supply Chain: CPO requires heterogeneous integration of CMOS, silicon photonics and III-V laser materials, resulting in low product yield. Micron-level alignment between optical fibers and waveguides raises manufacturing thresholds. The number of professional silicon photonic foundries is limited, keeping the mass-production cost at a relatively high level.
● Absence of Unified Industrial Standards: There is no universal specification for CPO mechanical interfaces, optical fiber standards and thermal control protocols, leading to significant differentiation among vendor solutions. Early adopters may face supplier lock-in risks and poor equipment compatibility. Organizations including OIF and OCI MSA are promoting the formulation of unified industrial standards.
● High Short-term Procurement Cost: Due to complex craftsmanship and low yield rate, the unit port cost of CPO is higher than traditional pluggable modules at the current stage. Nevertheless, CPO presents better cost performance for hyper-scale computing clusters when evaluating from the perspective of full life cycle including power consumption and expansion costs.
CPO Top Manufacturers and Industry Promoters (2025-2026)
The global CPO ecosystem consists of diverse manufacturers with distinct technical routes. Without unified industrial standards, different players jointly drive the technical iteration and commercial adoption of CPO. The key market participants are categorized as follows:
Leading CPO Manufacturers
These leading vendors own mature ASIC development capabilities and dominate the high-end CPO switch market, accelerating large-scale industrial deployment.
● Broadcom: As an early CPO developer, Broadcom released its third-generation 102.4 Tb/s TH6-Davisson CPO switch in late 2025, cutting power consumption by 70%. It initiated the OCI MSA to promote unified industry compatibility standards. The company adopts a dual-track strategy of CPO and pluggable switches to cover diverse data center demands.
● NVIDIA: NVIDIA tailors CPO solutions for GPU clusters. It launched Quantum-X InfiniBand and Spectrum-X Ethernet photonic switches at the 2025 GTC Conference. Leveraging TSMC COUPE 3D stacking technology, the switches feature detachable laser components for hot swapping. Scheduled for mass delivery in 2026, they enhance reliability for large-scale AI clusters.
● Marvell: Marvell develops switches and customized XPU accelerators. Its reference design integrates 6.4 Tb/s modular optical engines and detachable PIC couplers to simplify high-density fiber management. By embedding silicon photonic engines into computing chips, it supports cross-rack optical interconnection for both mid-range and high-end data centers.
Differentiated Innovative Players
These vendors focus on niche innovative tracks instead of mainstream switch markets, expanding the boundaries of chip-level optical interconnection.
● Ayar Labs: Ayar Labs skips switch-based architectures and develops direct chip-to-chip optical links. Its TeraPHY chip integrates optical I/O into AI accelerators complying with UCIe standards. Paired with 16-wavelength external lasers, it offers an efficient interconnection solution for next-generation high-performance GPUs.
Transitional & Conservative Vendors
These vendors adopt prudent strategies, either optimizing transitional optical solutions or reserving CPO technologies for future deployment.
● Cisco: It completed CPO prototype verification in 2023 and currently prioritizes yield optimization. With no clear commercial rollout plan, it awaits mature industry standards for large-scale deployment.
● Arista: It abandons in-house CPO development and promotes cost-effective LPO solutions for mid-tier general data centers, complementing high-end CPO products.
Key Supply Chain Enablers
Supply chain suppliers provide foundational components and manufacturing technologies to support CPO mass production:
● TSMC: Mass-produces the COUPE 3D stacking process in 2026, supporting high-end CPO products from NVIDIA and Broadcom.
● Corning: Supplies high-performance fiber connectors to ensure stable optical signal transmission.
● Lumentum and Coherent: Deliver multi-wavelength external laser sources for commercial CPO systems.
FiberMart CPO Solutions
Co-Packaged Optics (CPO) continues to gain traction as a transformative interconnection technology for AI computing infrastructure and hyperscale data centers. As a reliable global supplier, FiberMart provides high-performance fiber array components that support the large-scale commercial deployment of modern CPO systems.
FiberMart’s portfolio covers both standard Fiber Array Units and Polarization Maintaining Fiber Arrays. The high-precision FAUs ensure stable optical coupling between photonic chips and fiber circuitry, delivering consistent optical performance and long-term operational durability tailored for high-speed CPO transmission scenarios. Complementarily, PM fiber arrays are engineered for mainstream external laser source architectures, effectively stabilizing polarization states to accommodate the inherent sensitivity of silicon photonic devices. With versatile customizable configurations, FiberMart offers optimized, market-ready fiber array solutions to meet the growing demands of the global CPO ecosystem.
● High-precision FAU (Fiber Array Unit) for CPO System
● Polarization Maintaining Fiber Array (PM FA)
● Fiber Shuffle Cable for CPO Unit
Summary for CPO Technology in Data Center
CPO represents a critical architectural optimization rather than a simple technical iteration for data center interconnection. It fundamentally mitigates the inherent defects of traditional optical modules such as high power consumption, bandwidth limitation and signal distortion, becoming key hardware supporting million-scale GPU supercomputing clusters. Restricted by heat dissipation, maintenance, manufacturing and standardization constraints, CPO cannot achieve rapid popularization and will coexist with pluggable modules and LPO for the next decade.
With industrial maturity and continuous cost reduction after 2026, CPO will gradually penetrate from high-end computing scenarios to commercial data centers. In the long run, embedding optical engines directly into AI accelerators will become the industrial mainstream, blurring the boundary between electronics and photonics to lay a hardware foundation for general artificial intelligence and large-scale computing networks.
Frequently Asked Questions (FAQ)
Q1: What are the core differences between CPO and pluggable optical modules?
CPO integrates optical engines with ASICs to shorten electrical paths to millimeter level and remove DSP chips, achieving power consumption of 5-10 pJ/bit. Pluggable modules have an electrical path of 15-30 cm and rely on DSP for signal compensation with power consumption of 15-20 pJ/bit, while possessing advantages in hot swapping and maintainability.
Q2: Why do mainstream CPO products adopt external laser sources?
Lasers generate high heat and have relatively high failure rates. External placement realizes heat isolation and optimized thermal management. Meanwhile, independent hot swapping of lasers supports equipment maintenance without shutdown, improving system operational reliability.
Q3: Does CPO have high maintenance difficulty and failure rate?
The industry has optimized maintainability through technical improvements. Vendors such as NVIDIA adopt detachable photonic components to avoid integral replacement during failures. A 5%-10% port redundancy mechanism is applied to reduce single-point failure risks, enhancing the reliability of large-scale deployment.
Q4: Can LPO replace CPO as the mainstream solution?
LPO has cost and maintenance advantages in medium and low-speed commercial scenarios. Nevertheless, under ultra-high single-channel rates of 200G/400G, LPO is constrained by insufficient signal compensation capability and cannot match the extreme performance of CPO, serving only as a long-term transitional technology.
Q5: What are the functions of FAU and Fiber Shuffle in CPO packaging?
Fiber Array Unit (FAU) provides micron-level fixed fiber alignment to ensure low-loss and polarization-stable optical coupling between fibers and on-chip waveguides. Fiber Shuffle acts as an internal rearrangement array, optimizing disordered waveguide routing inside compact CPO packages. Together, they suppress optical crosstalk and improve mechanical stability under liquid cooling conditions, which are essential for high-density ELS-based CPO architectures.
Q6: What is the biggest bottleneck limiting large-scale CPO mass adoption?
At this stage, the primary restriction comes from supply chain immaturity and inconsistent industrial standards. Heterogeneous integration of multiple materials leads to low packaging yield and high manufacturing costs. In addition, non-uniform mechanical interfaces among vendors cause compatibility risks. Without unified MSA specifications and mature passive optical components, CPO will remain limited to small-scale deployment in high-end AI clusters.
Posted on 18 May, 2026, by Francisco, Fibermart, All Copy Right Reserved.
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